1. Field of the Invention
The present invention relates to sensor elements obtained by using, for example, technologies for semiconductors and micro electro mechanical systems (hereinafter, referred to as MEMS).
2. Description of the Related Art
In recent years, sensor devices introduce microfabrication and techniques which apply technologies for semiconductors and MEMS and tend to have more sensitive and complicated structures. Among the sensor devices, examples of sensor elements each having a thin film hollow structure include, for example, a pressure sensor, an ultrasonic sensor, and a flow sensor.
Such sensor elements are formed from a wafer and are each provided with a cavity that is formed just below a wafer main surface on which wiring, circuit, and the like are provided. The cavity is formed by, for example, deep dug etching using inductively coupled plasma-reactive ion etching (hereinafter, referred to as ICP-RIE) from the back surface of the element or wet etching by chemical solution of potassium hydroxide (referred to as KOH) and tetra methyl ammonium hydroxide (referred to as TMAH). For example, in the case of the pressure sensor, a diaphragm in which a detection unit is supported on the cavity by thin film stress control is provided.
Furthermore, the pressure sensor includes a capacitance type, which converts a change in electrostatic capacitance to an electrical signal and detects, a piezoresistance type, and the like. The piezoresistance type is formed with a Wheatstone bridge circuit including a plurality of piezoresistances in the diaphragm. The piezoresistance type pressure sensor uses a function, which converts a change in resistance of the piezoresistance to an electrical signal and detects, for the sensor, the resistance change of the piezoresistance being caused by external pressure. Incidentally, the piezoresistance type pressure sensor includes a differential pressure sensor and an absolute pressure sensor that measures absolute pressure by airtight sealing the cavity by a base.
Next, the structure of a conventional absolute pressure sensor element 100 will be described with reference to FIGS. 7A to 7C. First, FIG. 7A is a structural plan view in which the conventional sensor element 100 is seen from the top side.
The sensor element 100 includes piezoresistances 4, terminal pads 7, wiring 5 connected thereto, an insulating film 6, and the like. Furthermore, a dotted line in the drawing shows the position of a diaphragm 9. Furthermore, all four piezoresistances 4 provided in the drawing are formed in the diaphragm 9.
Further, a cavity 8a is formed just below the diaphragm 9 and the cavity 8a is airtight sealed under vacuum. Incidentally, reference numeral 16 denotes a scratch occurred on the back surface side of a silicon on insulator (hereinafter, referred to as SOI) wafer 10 and the scratch 16 reaches from the cavity 8a to the cut surface of the sensor element 100. 17 denotes an attached foreign material remained on the back surface of the SOI wafer 10. Incidentally, the structural plan view of the sensor element 100 shows a shape being cut and separated by dicer cutting or the like.
Next, FIG. 7B is a view of a hypothetical cross-sectional structure showing the structure of the sensor element 100 obtained by cutting an A-A′ porion of a dashed-dotted line shown in the structural plan view of FIG. 7A. The sensor element 100 has a structure in which a base 11 of another glass wafer is bonded to the SOI wafer 10 and the cavity 8 is formed inside thereof. 13 denotes a fitting portion.
Next, a Wheatstone bridge circuit composed of the piezoresistances 4 and the wiring 5 provided on the diaphragm 9 is formed on the main surface of the SOI wafer 10. The Wheatstone bridge circuit is coated with the insulating film 6. Incidentally, a gap due to the scratch 16 simulates the scratch occurred on the fitting portion 13 on the back surface side of the SOI wafer 10.
Next, a view of a hypothetical cross-sectional structure of FIG. 7C will be described. The cross-sectional structural view shows a cross-sectional structure of the structure of the sensor element 100 obtained by cutting a B-B′ portion of a dashed-dotted line shown in the structural plan view of FIG. 7A, as in FIG. 7B. 17 simulates the attached foreign material remained on the fitting portion 13. Furthermore, the drawing images a state where the attached foreign material 17 becomes a bump and accordingly the fitting portion 13 floats thereon.
Next, processes for obtaining the structure of the conventional sensor element 100 will be described in numerical order along a flow chart of FIGS. 8A to 8F. FIGS. 8A to 8F show a process flow chart of the hypothetical cross-sectional structure of the structure of the sensor element 100 obtained by cutting a C-C′ portion of a dashed-dotted line shown in the structural plan view of FIG. 7A.
First, reference numeral 10 of this process flow chart denotes an SOI wafer, which is a special wafer that includes: an n-type active layer 1 in which plane orientation on the upper side of the main surface is (100), the n-type active layer 1 being made of silicon or the like; an embedded oxide film 2; and a supporting substrate 3 on the back surface side. The SOI wafer 10 is manufactured by, for example, UNIBOND that is smart cut technology or separation by implanted oxygen (referred to as SIMOX). In FIG. 8A, piezoresistances 4 and terminal pads 7 formed on the SOI wafer 10 by the impurity diffusion method or the ion implantation method are formed at the positions shown in the drawing.
Next, an insulating film 6 is coated on the main surface of the SOI wafer 10 (FIG. 8B). Incidentally, the insulating film 6 is coated on the whole of the main surface of the SOI wafer 10 by using a method of sputtering or chemical vapor deposition (hereinafter, referred to as CVD). In the process coated with the insulating film 6, the insulating film 6 is also coated on the terminal pads 7; and therefore, etching processing for opening the terminal pads 7 is needed. First, a resist mask is provided on a region other than an opening portion of the terminal pad 7; and then, unnecessary insulating film 6 provided on the terminal pad 7 is removed by dry etching using mixed gas of, for example, fluorine based gas and oxygen (O2). This process is performed and accordingly a structural cross-sectional view of FIG. 8B is obtained.
Processing anchored by the processing of the back surface side of the SOI wafer 10 is performed in the subsequent processing of FIG. 8C. In FIG. 8C, processing for coating both surfaces of the SOI wafer 10 with masks is performed. First, a protecting mask 14 is formed on the main surface of the SOI wafer 10. The protecting mask 14 is intended to protect the main surface; and therefore, for example, coating with the resist may be performed on the whole surface.
Next, patterning of a back side mask 15 for forming a cavity 8a on the back surface of the SOI wafer 10 is performed by photosensitive agent such as the resist. First, resist coating is performed. Next, an exposure superimposed with the mask is performed by equipment such as a double sided aligner by utilizing an alignment mark on the main surface; finally, processing procedure is performed in developing solution and accordingly a pattern of an opening portion 12 is obtained.
Next, in FIG. 8D, deep dug etching using ICP-RIE is performed from the back surface side of the SOI wafer 10. This etching is performed; and accordingly, the cavity 8a is formed just below a diaphragm 9. Incidentally, as shown in the drawing, the back side mask 15 becomes thinner than the original film thickness because of being exposed to plasma by the ICP-RIE etching processing for a long time. Therefore, a material to be selected for the back side mask 15 is required for an etching selective ratio with silicon, and it is important to select the film thickness or material of the back side mask 15, the film thickness needing quantity as much as quantity not to be vanished away in the process being dug down from the supporting substrate 3 to the embedded oxide film 2.
Next, in FIG. 8E, the protecting mask 14 and the back side mask 15 coated on both surfaces of the SOI wafer 10 are removed by using a processing method such as a plasma ashing apparatus using oxygen gas and resist stripping solution. Process processing of the back surface of the SOI wafer 10 is completed through the above processing. Finally, bonding to a base 11 is performed in FIG. 8F; and accordingly, the structure of the conventional sensor element 100 is obtained.
Incidentally, reference numeral 13 in FIG. 8F denotes a fitting portion. As shown in the drawing, all the back surface of the SOI wafer 10 other than the cavity 8a is utilized as the fitting portion 13. In addition, a process of a piezoresistance type pressure sensor element using an SOI wafer 10 is introduced in Japanese Unexamined Patent Publication No. 2008-190970.